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PD75112(A), 75116(A) 4-Bit Single Chip-Microcomputer
Data Sheet
Description
The PD75116(A) is one of the 4-bit single-chip microcomputer 75X series. The PD75116(A) is a product with the extended ROM capacity of the PD75108(A). In addition of high-speed operations, it can manipulate data in units of 1, 4 and 8 bits. In particular, the I/O operation of the PD75116 have been improved by a wide variety of bit control instructions. The PD75116 is provided with interface inputs/outputs with peripheral circuits having different power voltages, and analog inputs and suitable for controlling automobile electrical equipment, etc. For the PD75116(A), an on-chip pin-compatible one-time PROM product (PD75P116) is separately available for system development evaluation. Functions are described in detail in the following User's Manual, which should be read when carrying out design work. PD751xx Series User's Manual: IEM-992
Ordering Code Package Qualty Grade Special Special Special Special
PD75112CW(A)-xxx
64-pin plastic shrink DIP (750 mil) PD75112GF(A)-xxx-3BE 64-pin plastic QFP (14 x 20 mm) 64-pin plastic shrink DIP PD75116CW(A)-xxx (750 mil) PD75116GF(A)-xxx-3BE 64-pin plastic QFP (14 x 20 mm) Remarks: xxx is a ROM code number.
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Unless there are any particular functional differences, the PD75116(A) is described in this document as a representative product.
Features
* Higher reliability than PD75116 * Architecture "75X" equivalent to 8-bit microcomputer * Minimum instruction execution time (high-speed operation): 0.95 s (when operated at 4.19 MHz and 5 V) * Instruction execution variable function: 0.95s/1.91s/ 15.3 s (when operated at 4.19 MHz) * Many input/output ports: 58 * 3-channel on-chip 8-bit timers * 8-bit on-chip serial interface * Multi-interruptible vector interrupt function
Applications
Automobile electrical equipment, etc.
The information in this document is subject to change without notice. The mark
5 shows major revised points.
Document No. IC-2811A (O. D. No. IC-8261A) Date Published March 1994 P Printed in Japan
(c)NEC Corporation 1990
PD75112(A), 75116(A)
Defferences between PD75112(A), 75116(A) and PD75112, 75116
Product Name Item Quality grade Electrical specifications Absolute maximum ratings DC characteristics Direct LED drive Special
PD75112(A), 75116(A)
Standard
PD75112, 75116
Different high-level output current and low-level output current Different low-level output voltage Not possible Possible
Outline of Functions
Item No. of basic instruction Min. instruction execution time On-chip memory ROM RAM General register Accumulator 43 0.95 s/1.91 s/15.3 s (when operated at 4.19 MHz), switchable at 3 levels 12160 x 8 (PD75112(A)), 16256 x 8 (PD75116(A)) 512 x 4 4 bits x 8 x 4 banks (memory mapping) Three accumulated in compliance with controlled date lengths *1-bit accumulator (CY), 4-bit accumulator (A), 8-bit accumulator (XA) 58 in total * CMOS input pin : 10 * CMOS input/output pin (LED direct drive enable) : 32 * Intermediate withstand voltage N-ch open drain : 12 input/output pin (bit-wise pull-up resistor inscorporation possible) * Comparator input pin (4-bit accuracy) : 4 * 8-bit timer/event counter x 2 * 8-bit basic interval timer (applicable to watchdog timer) * 8-bits * First LSB/first MSB switchable * Two transfer modes (transmit and receiver/receive dedicated mode) External : 3, External : 2 * STOP/HALT mode -40 to +85C 2.7 to 6.0 V * On-chip power-on reset circuit (mask option) * On-chip bit contol memory (bit sequential buffer) * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm) Internal : 4 Description
Input/output port
Timer/counter
Serial interface
Vector interrupt Test input Standby Operating temperature range Operating voltage Others
Package
2
PD75112(A), 75116(A)
CONTENTS 1. 2. 3. Pin Configuration (Top View)............................................................................................... 4 Block Diagram......................................................................................................................... 6 Pin Functions.........................................................................................................................
3.1 3.2 3.3 3.4 3.5
7
Port Pins...................................................................................................................................................... 7 Non-Port Pins............................................................................................................................................... 8 Pin Input/Output Circuits............................................................................................................................ 9 Recommended Connection of Unused Pins............................................................................................. 10 Caution Relating to Use of P00/INT4 Pin and RESET Pin........................................................................ 10
4. 5.
Memory Configuration............................................................................................................. 11 Peripheral Hardware Functions.............................................................................................. 14
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Digital Input/Output Port......................................................................................................................... 14 Clock Generator......................................................................................................................................... 14 Clock Output Circuit.................................................................................................................................. 16 Basic Interval Timer.................................................................................................................................... 16 Timer/Event Counter................................................................................................................................. 17 Serial Interface............................................................................................................................................ 19 Programmable Threshold Port (Analog Input Port)............................................................................... 21 Bit Sequential Buffer................................................................................................................................... 22 Power-On Flag (Mask Option).................................................................................................................... 22
6. 7. 8. 9.
Interrupt Functions.................................................................................................................. 23 Standby Functions ............................................................................................................... 25 Reset Functions..................................................................................................................... 26 Instruction Set....................................................................................................................... 29
10. Mask Option Selection.......................................................................................................... 37 11. Electrical Specifications........................................................................................................ 38 12. Package Information ............................................................................................................ 48 13. Recommended Soldering Conditions ................................................................................. 51 APPENDIX A. Diffeences between PD751xx(A) Series Products and Related PROM Products.............................................................................. 52 APPENDIX B. Development Tools ............................................................................................ 53 APPENDIX C. Related Documentations ................................................................................... 54
3
PD75112(A), 75116(A)
1. Pin Configuration (Top View)
64-Pin Plastic Shrink DIP (750 mil)
P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 PTH01 PTH00 TI0 TI1 P23 P22/PCL P21/PTO1 P20/PTO0 P03/SI P02/SO P01/SCK P00/INT4 P123 P122 P121 P120 P133 P132 P131 P130 P143 P142 P141 P140 NC VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS P90 P91 P92 P93 P80 P81 P82 P83 P70 P71 P72 P73 P60 P61 P62 P63 X1 X2 RESET P50 P51 P52 P53 P40 P41 P42 P43 P30 P31 P32 P33
PD75112CW(A)-xxx PD75116CW(A)-xxx
4
PD75112(A), 75116(A)
64-Pin Plastic QFP (14 x 20 mm)
P140
P141
P142
P143
P41 P40 P53 P52 P51 P50 RESET X2 X1 P63 P62 P61 P60 P73 P72 P71 P70 P83 P82
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
64 63 62 61 60 59 58 57 56 55 54 53 52
P130
P42
P43
P30
P31
P32
P33
VDD
NC
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P131 P132 P133 P120 P121 P122 P123 P00/INT4 P01/SCK P02/SO P03/SI P20/PTO0 P21/PTO1 P22/PCL P23 T11 T10 PTH00 PTH01
20 21 22 23 24 25 26 27 28 29 30 31 32
P13/INT3
P12/INT2
P11/INT1
P10/INT0
PTH03
Pin Name 5
P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 P90-P93 P120-P123 P130-P133 P140-P143 : : : : : : : : : : : : : Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port8 Port9 Port12 Port13 Port14 SCK SO SI PTO0, PTO1 PCL PTH00-PTH03 INT0, INT1, INT4 INT2, INT3 TI0, TI1 X1, X2 RESET NC VDD VSS : : : : : : : : : : : : : : Serial Clock Serial Output Serial Input Programmable Timer Output Programmable Clock Programmable Threshold Input External Vectored Interrupt Input External Test Input Timer Input Clock Oscillation Reset No Connection Positive Power Supply Ground
PTH02
PD75116GF(A)-xxx-3BE
PD75112GF(A)-xxx-3BE
P81
P80
P93
P92
P91
P90
VSS
5
6
BIT SEQ. BUFFER(16) BASIC INTERVAL TIMER INTBT TI0 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 TI1 PTO1/P21 TIMER/EVENT COUNTER #1 INTT1 SI/P03 SI/P02 SCK/P01 INTSIO INT0/P10 INT1/P11 INT2/P12 INT3/P13 INT4/P00 CLOCK OUTPUT CONTROL INTERRUPT CONTROL fX/2 N PORT12 4 P120-P123 PORT9 4 P90-P93 16256 x 8 BITS ( PD75116(A)) SERIAL INTERFACE ROM PROGRAM MEMORY 12160 x 8 BITS ( PD75112(A)) DECODE AND CONTROL DATA MEMORY 512 x 4 BIT PORT6 4 P60-P63 PORT5 RAM 4 P50-P53 GENERAL REG. PORT4 4 P40-P43 PORT3 4 P30-P33 PROGRAM COUNTER (14) ALU CY SP (8) PORT1 4 P10-P13 PORT0 4 P00-P03 BANK PORT2 4 P20-P23 PORT7 4 P70-P73 PORT8 4 P80-P83 PTH00-PTH03 4 PROGRAMMABLE THRESHOLD PORT # 0 CLOCK DIVIDER CLOCK GENERATOR STAND BY CONTROL CPU CLOCK
2. Block Diagram
PD75112(A), 75116(A)
PORT13 4 P130-P133
PCL/P22
X1
X2
PORT14 VDD VSS RESET
4
P140-P143
PD75112(A), 75116(A)
3. Pin Functions
3.1 Port Pins
Pin Name Input/ Output Dual Function Pin INT4 SCK SO SI INT0 INT1 INT2 INT3 Input/output PTO0 PTO1 PCL 4-bit input/output port (PORT2)
x
Function
8-Bit I/O
x
At Reset Input
I/O Circuit Type *1 B F E B
P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 to P33
Input Input/output Input/output Input Input
4-bit input port (PORT0)
4-bit input port (PORT1)
Input
B
Input
E
Input/output
Programmable 4-bit input/output port (PORT3) Bit-wise input/output setting enable 4-bit input/output port (PORT4) 4-bit input/output port (PORT5) Programmable 4-bit input/output port (PORT6) Bit-wise input/output setting enable 4-bit input/output port (PORT7) 4-bit input/output port (PORT8) 4-bit input/output port (PORT9) N-ch open drain 4-bit input/ output port (PORT12) Bit-wise pull-up resistor incorporation enable (mask option) 2 V withstand for open drain N-ch open drain 4-bit input/ output port (PORT13) Bit-wise pull-up resistor incorporation enable (mask option) 12 V withstand for open drain N-ch open drain 4-bit input/output port (PORT14) Bit-wise pull-up resistor incorporation enable (mask option) 12 V withstand for open drain
q q q q
Input
E
P40 to P43 P50 to P53 P60 to P63
Input/output Input/output Input/output
Input Input Input
E E E
P70 to P73 P80 to P83 P90 to P93 P120 to P123
Input/output Input/output Input/output Input/output
Input Input Input Input*2
E E E M
P130 to P133
Input/output
Input*2
M
P140 to P143
Input/output
Input*2
M
* 1: Circles indicate Schmitt trigger inputs.
2: High impedance for open drain High level for on-chip pull-up resistors
7
PD75112(A), 75116(A)
3.2 Non-Port Pins
Input/Output Dual Function Pin Function At Reset I/O Circuit Type*1 N B
PTH00 to PTH03 TI0 TI1 PTO0 PTO1 SCK SO SI INT4 INT0 INT1 INT2 INT3 PCL X1, X2
Input Input
Threshold voltage ariable 4-bit analogy input port. External event pulse input for the timer/event counter or edge detect vector interrupt input. 1-bit input enable.
Input/output
P20 P21
Timer/event counter output.
Input
E
Input/output Input/output Input Input
P01 P02 P03 P00 P10 P11
Serial clock input/output. Serial data output. Serial data input. Edge detect vector interrupt input (for detecting both rising and falling edges). Edge detect vector interrupt input (detected edge selectable).
Input Input Input Input
F E B B
Input
Input
B
Input
P12 P13
Edge detect testable input (for rising edge detection).
Input
B
Input/output
P22
Clock output. Crystal/ceramic connect pin (system clock oscillation). In case with the external clock, input a signal to X1 and the antiphase to X2.
Input
E
RESET NC*2 VDD VSS
Input
System reset input (low level active). No Connection Positive power supply. GND potential.
B
* 1: Circles indicate Schmitt trigger inputs. 2: When the PWB is shared with the PD75P116, connect the NC pin to VDD directly.
8
PD75112(A), 75116(A)
3.3 Pin Input/Output Circuits PD75116(A) pin input/output crcuit are shown in schematic form.
Figure 3-1 Pin Input/Output Circuits
Type F
data Type D IN/OUT
Type A
VDD
P-ch IN N-ch
output disable
Type B
CMOS specified input buffer
Input/output circuit consisting of a Type D push-pull output and a Type B Schmitt-triggered input.
Type B Type M
IN
VDD
Pull-Up Register (Mask Option) Schmitt triggered-input with hysteresis characteristics
IN/OUT
Type D
VDD data P-ch OUT output disable N-ch
data output disable
N-ch (+6 V Withstand)
Middle-High Voltage Input Buffer (+6 V Withstand)
Push-pull output which can be set at output high impedance (with both P-ch an N-ch set to OFF)
Type N Comparator
Type E
IN
data Type D output disable IN/OUT
+ -
Type A
VREF (Threshold Voltage) Input/output circuit consisting of a Type D push-pull output and a Type A input buffer
9
PD75112(A), 75116(A)
3.4 Recommended Connection of Unused Pins
Pin PTH00 to PTH03 TI0 TI1 P00 P01 to P03 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P73 Connect to VSS Connect to VSS or VDD Connect to VSS Input state : Connect to VSS or VDD Output state : Leave open Recommended Connecting Method Connect to VSS or VDD
3.5 Caution Relating to Use of P00/INT4 Pin and RESET Pin In addition to the functions described in sections 3.1 and 3.2, the P00/INT4 pin and the RESET pin have the function to set the IC test mode for testing the PD75116(A) internal operations. When a voltage larger than VDD is applied to one of these two pins, the test mode is set. Thus, if noise exceeding VDD is applied even during normal operations, the test mode is set and normal operations may be discontinued. For example, if a cable from the P00/INT4 or RESET pin is too long, inter-wiring noise may be applied to the pin, the pin voltage may become larger than VDD, causing malfunctioning. Thus, carry out wiring to minimize inter-wiring noise. If the noise cannot be suppressed completely, carry out the following countermeasure against noise using an externally mounted component. o Connect a diode with low VF (max 0.3 V)between VDDs
P80 to P83
VDD
P90 to P93 P120 to P123 P130 to P133
P00/INT4, RESET
Diode with low VF
VDD
P140 to P143 RESET NC Connect to VDD*1 Leave open or connect to VDD*2
o Connect acapacitor between VDDs
*1: Only when a power-on reset generator is built in by mask option, connect t VDD. 2: When the PWB is shared with the PD75P116, connect the NC pin to VDD directly.
VDD
VDD P00/INT4, RESET
10
PD75112(A), 75116(A)
4. Memory Configuration
* Program Memory (ROM) 12160 x 8 bits (0000H to 2F7FH): PD75112(A) 16256 x 8 bits (0000H to 3F7FH): PD75116(A) * 0000H to 0001H: Vector table for writing the program start address by reset * 0002H to 000BH: Vector table for writing the program start address by interrupt * 0020H to 007FH: Table area to be referred to by the GETI instruction * Data Memory * Data area 512 x 4 bits (000H to 1FFH) * Peripheral hardware area 128 x 4 bits (F80H to FFFH)
Figure 4-1 Program Memory Map (PD75112(A))
Address
7 0000H 0002H 0004H 0006H 6
Internal Reset Start Address (Low-Order 8 Bits)
0
MBE RBE Internal Reset Start Address (High-Order 6 Bits) MBE RBE INTBT/INT4 Start Address
INTBT/INT4 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) BR !addr Instruction Branch Address CALLF ! faddr Instruction Entry Address CALL !addr Instruction Subroutin Entry Address
MBE RBE INT0/INT1 Start Address
INT0/INT1 Start Address
MBE RBE INTSIO Start Address
INTSIO Start Address
0008H
MBE RBE INTT0 Start Address
INTT0 Start Address
000AH
MBE RBE INTT1 Start Address
INTT1 Start Address
0020H
GETI Instruction Reference Table
BRCB ! caddr Instruction Branch Address
BR $addr Instruction Relative Branch Address (-15 to +16)
007FH 0080H 07FFH 0800H 0FFFH 1000H

BRCB !caddr Instruction Branch Address
Branch Address Subroutine Entry Address by GETI Instruction
1FFFH 2000H
BRCB !caddr Instruction Branch Address
2F7FH
Remarks: In all other cases, the program can be branched by the BR PCDE and BR PCXA
instructions to an address with only the lower 8 bits of PC changed. 11
PD75112(A), 75116(A)
Figure 4-2 Program Memory Map (PD75116(A))
Address 7
0000H 0002H 0004H 0006H
0 6 MBE RBE Internal Reset Start Address (High-Order 6 Bits)
Internal Reset Start Address (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (High-Order 6 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) CALLF ! faddr Instruction Entry Address CALL !addr Instruction Subroutin Entry Address
MBE RBE INTBT/INT4 Start Address
INTBT/INT4 Start Address
MBE RBE INT0/INT1 Start Address
INT0/INT1 Start Address
MBE RBE INTSIO Start Address
INTSIO Start Address
0008H
MBE RBE INTT0 Start Address
INTT0 Start Address
000AH
MBE RBE INTT1 Start Address
INTT1 Start Address
0020H
GETI Instruction Reference Table
BRCB ! caddr Instruction Branch Address
BR !addr Instruction Branch Address
007FH 0080H 07FFH 0800H 0FFFH 1000H

BRCB !caddr Instrucion Branch Address
BR $addr Instruction Relative Branch Address (-15 to -1 +2 to +16)
Branch Address Subroutine Entry Address by GETI Instruction
1FFFH 2000H
BRCB !caddr Instrucion Branch Address
2FFFH 3000H
BRCB !caddr Instruction Branch Address
3F7FH
Remarks: In all other cases, the program can be branched by the BR PCDE and BR PCXA instructions to an address with only the lower 8 bits of PC changed.
12
PD75112(A), 75116(A)
Figure 4-3 Data Memory Map
Data Memory 000H General Regoster Area 01FH (32 x 4)
Memory Bank
Bank 0
Stack Area Data Area Static RAM (512 x 4) 256 x 4
0FFH 100H 256 x 4 1FFH Bank 1
Not Incorporated
F80H
Peripheral Hardware Area
128 x 4
Bank 15
FFFH
13
PD75112(A), 75116(A)
5. Peripheral Hardware Functions
5.1 Digital Input/Output Port The digital input/output port has the following tree types. * CMOS input (PORT0, 1) :8 * CMOS input/output (PORT 2 to PORT 9) : 32 * N-ch open-drain input/output (PORT 12 to PORT 14): 12 Total 52
Table 5-1 Functions of Digital Ports
Port (Code) PORT0 PORT1 PORT3 PORT6 PORT2 PORT4 PORT5 PORT7 PORT8 PORT9 PORT12 PORT13 PORT14
Functions 4-bit input
Operations and Features Read or test always enable irrespectively of the operating mode of dual-function pins. Can be set bit-wise to the input or output mode.
Remarks Share the pins with SI, SO, SCK and INT0 to 4.
4-bit input/ output
Can be set in 4-bit units to the input or output mode. Ports 4 and 5, 6 and 7, 8 and 9 can form pairs and data can be input/output in 8-bit units.
Port 2 shares the pin with PTO0, PTO1 and PCL.
4-bit input/ output (N-ch opendrain, 12 V withstand voltage)
Can be set in 4-bit units the input or output mode. Ports 12 and 13 can form a pair and data can be input/output in 8bit units.
On-chip pull-up registers can be specified bit-wise by mask option.
5.2 Clock Generator The clock generator is a circuit which supplies the CPU and peripheral hardware with various clocks and controls the CPU operating mode. The instruction execution time can be changed. * 0.95 s/1.91 s/15.3 s (at 4.19 MHz operation)
14
PD75112(A), 75116(A)
Figure 5-1 Block Diagram of Clock Generator 5
* Basic Interval Timer (BT) * Clock Generator * Timer/Event Counter * Serial Interface * Clock Output Circuit
1/8 to 1/4096 System Clock Oscillator fxx or fx 1/2 1/16 Oscillation Stop Selector PCC PCC0 Frequency Divider
Frequency Divider 1/4

* CPU * Clock Output Circuit
PCC1 Internal Bus 4 PCC2 HALT* PCC3 STOP* R Q HALT F/F S
PCC2, PCC3 Crear
STOP F/F Q S
Wait Release Signal from BT RES(Internal Reset) Signal Standby Release Signal from the Interrupt Control Circuit
R
Remarks 1: 2: 3: 4: 5: 6:
fXX=crystal/ceramic oscillator frequency. fX=external clock frequency. =CPU clock *indicates instruction execution. PCC (processor clock control register) 1 clock cycle (tCY) of is 1 michine cycle of the instruction. For tCY, see the AC characteristics in the 11."Electrical Specifications".
15
PD75112(A), 75116(A)
5.3 Clock Output Circuit The clock output circuit is a circuit to generate clock pulses from the P22/PCL pin. It is used to supply the peripheral LSIs with clock pulses. *Clock output (PCL):, 524 kHz, 262 kHz (at 4.19 MHz operation) The clock output cicuit configuration is shown as the following.
Figure 5-2 Clock Output Circuit Configuration
From the Clock Generator
3
Output Buffer Selector P22/PCL
fxx/2
fxx/2
4
PORT2.2 P22 Output Latch
PMGB Bit 2 Port 2 Input/ Output Mode Specification Bit
CLOM3
0
CLOM1 CLOM0 CLOM
4 Internal Bus
5.4 Basic Interval Timer The basic interval timer has the following functions; * Interval timer operation to generate reference time interrupts * Watchdog timer application to detect program overrun * Wait time selection and count when the standby mode is released * Count content read
16
PD75112(A), 75116(A)
Figure 5-3 Basic Interval Timer Configuration
From the Clock Generator fxx/2 5
Clear
Clear
fxx/2 7 MPX fxx/2
9
Basic Interval Timer (8-Bit Frequency Divider)
Set
BT Interrupt Request Flag
fxx/2 12
BT
IRQBT
Vector Interrupt Request Signal
3 3
Wait Release Signal When the Standby Mode is Released BTM0 BTM
BTM3
BTM2
BTM1
*SET1
4 Internal Bus
8
Remark: * indicates instruction execution.
5.5 Timer/Event Counter The PD75116(A) has a two-channel on-chip timer/ event counters. Channels 0 and 1 of the timer/event counter have the same configuration and functions. They differ only in the selectable count pulse (CP) and the function of supplying clocks to the serial interface. The timer/event counter has the following functions: * Programmable interval timer operation * Output of square wave having any selected frequency to PTOn pin * Event counter operation * Use of TIn pin as an external interrupt input pin * Output of TIn pin input divided by N to PTOn pin (frequency divider operation) * Serial shift clock supply to the serial interface circuit (channel 0 only) * Count status read function
17
18
Internal Bus 8 *1 SET 1 TMn 8 8 TMODn TOEn TO Enable Flag TOFn TOn PORT2.n P2n Output Latch TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0 TIn 8 Modulo Register (8) PGMB Bit 2 Port2 Input/ Output Mode *3 To Serial Interface Comparator (8) Input Buffer TIn *2 From Clock Generator Count Register (8) MPX CP Clear Edge Detector 8 Tn INTTn IRQTn Set Signal Match TOUT F/F TO Selector Output Buffer P2n/PTOn Timer Operation Start RES TMn1 TMn0 IRQTn Clear Signal
Figure 5-4 Block Diagram of Timer/Event Counter (n=0, 1)
PD75112(A), 75116(A)
* 1: SET1: Instruction execution 2: Refer to Figure 5-1 3: Only channel 0 of the time/event counter can output a signal to the serial interface
PD75112(A), 75116(A)
5.6 Serial Interface The PD75116(A) incorporates the clock synchronous 8-bit serial interface. The serial interface has the following two modes. * Operation stop mode * 3-wire serial I/O mode (MSB/LSB top switching possible) Connection with the PD75116(A) and the 75X series, 78K series and various I/O devices is possible in the 3wire serial I/O mode.
19
20
Internal Bus 8 8 SIO0 P03/SI Shift Register (8) SIO7 SIO SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0 8 SET1 * SIOM P02/SO Over Flow Serial Clock Counter (3) INTSIO IRQSIO Set Signal Serial Start IRQSIO Clear Signal Clear P01/SCK R Q S
Figure 5-5 Block Diagram of Serial Interface
PD75112(A), 75116(A)
fxx/2 MPX
4
fxx/210 TOF 0 (From Timer Channel 0)
*: SET1: Instruction execution
PD75112(A), 75116(A)
5.7 ProgrammableThreshold Port (Analog Input Port) The PD75116(A) is equipped with 4-bit analog input pins (PTH00 to PTH03) capable of changing the threshold voltage. These pins are configured as shown in Figure 5-6. Sixteen threshold voltage (VREF) values (VDD x 0.5 -VDD x 16 15.5 16 ) are available and analog signals can be directly input. The analog input port can also be used as a digital 7.5 signal input port by selecting VDD x 16 for VREF.
Figure 5-6 Block Diagram of Programmable Threshold Port
Input Buffer PTH00 + -
PTH01
+ -
PTH02
+ -
Programmable Threshold Port Input Latch (4)
PTH03
+ - Operation Stop VDD PTHM7 PTH0
Internal Bus
1 R 2 R
PTHM6 PTHM5
R MPX VREF PTHM4 8 PTHM3 1 R 2 4 PTHM2 PTHM1 PTHM0 PTHM
21
PD75112(A), 75116(A)
5.8 Bit Sequential Buffer ... 16 bit The bit sequential buffer is a special data memory for bit control. Since this buffer can easily operate bits by sequentially changing address and bit specifications, it can be conveniently be used for bit-wise processing of data having long bit lengths.
Figure 5-7 Bit Sequential Buffer Format
Address Bit Symbol 3
FC3H 2 1 0 3
FC2H 2 1 0 3
FC1H 2 1 0 3
FC0H 2 1 BSB0 0
BSB3
BSB2
BSB1
L Register
L=F
L=C L=B
L=8 L=7 DECS L INCS L
L=4 L=3
L=0
Remarks: In pmen. @L addressing, the specified bit moves in accordance with the L register.
5.9 Power-On Flag (Mask Option) The power-on flag (PONF) is only set (1) when the power-on reset circuit is activated and the power-on reset signal is generated (see Figure 8-1). PONF is mapped on bit 0 at address FD1H of the data memory space and is manipulated by a bit manipulation instruction However, it cannot be set(1) by the SET1 instruction.
22
PD75112(A), 75116(A)
6. Interrupt Functions
There are seven types of interrupt sources for the PD75116(A) to allow multi-interruption with priority. The PD75116(A) is also provided with two types of edge detection testable inputs. The PD75116 interrupt control circuit has the following functions; * Hardware controlled vector interrupt function which enables to control by the interrupt enable flag (IExxx) and the interrupt master enable flag (IME) whether an interrupt should be enabled. * Interrupt start address can be set freely. * Multiple interrupt function which enables to specify priority by the interrupt priority select register (IPS). * Interrupt request flag (IRQxxx) test function (interrupt generation can be checked by the software). * Standby mode release (the interrupt to be released can be selected by the interrupt enable flag).
23
24
Internal Bus 2 IM1 2 IM0 9 Interrupt Enable Flag (IE x x x) (IME) 4 IPS 2 IST INT BT INT4 /P00 INT0 /P10 INT1 /P11 Edge Detection Circuit Edge Detection Circuit Edge Detection Circuit INTSIO IRQBT Decoder IRQ4 IRQ0 IRQ1 Priority Control Circuit IRQSIO Vector Table Address Generator INTT0 IRQT0 INTT1 INT2 /P12 INT3 /P13 Edge Detection Circuit Edge Detection Circuit IRQT1 IRQ2 Standby Release Signal IRQ3 Interrupt Request Flag
Figure 6-1 Block Diagram of Interrupt Control Circuit
PD75112(A), 75116(A)
PD75112(A), 75116(A)
7. Stanby Functions
Two types of standby modes (STOP and HALT modes) are available for the PD75116(A) to decrease power consumption during standby for program.
Table 7-1 Operation Statuses in Standby Mode
STOP Mode Set instruction Operation status Clock generator Basic interval timer STOP instruction Clock oscillation stop Operation stop HALT Mode HALT instruction Only CPU clock stop Operation (IRQBT set at reference time intervals) Operation enabled when aclock other than is specified for the serial clock
Serial interface
Operation enabled only when external SCK input and TO0 clock are set for serial clocks (when timer/event counter 0 is set to external TI0 input) is selected Operation enabled only when TIn pin input is specified for the count clock Operation stop
Timer/event counter
Operation enabled Clock other than CPU clock enabled for output Operation stop
Clock output circuit
CPU Release signal
Operation stop
Interrupt request signal enabled by interrupt enable flag or RESET input
25
PD75112(A), 75116(A)
8. Reset Functions
The reset signal (RES) generator is configured as shown in Figure 8-1.
Figure 8-1 Reset Signal Generator
RESET
Internal Reset Signal (RES)
Mask Option Power-On Reset Circuit
SWB
SWA
Power-On Flag(PONF)
Bit Control Instruction Execution *
Internal Bus
*:
PONF setting (1) by SET1 instruction is not possible.
26
PD75112(A), 75116(A)
The power-on reset circuit generates the internal reset signal by rising of supply voltage. This pulse is used in the three ways according to the specification of mask option of SWA and SWB shown in Figure 8-1 (refer to "10. Mask Option Selection"). Reset operations are shown in Figures 8-2 and 8-3.
Figure 8-2 Reset Operation by Power-on Reset
Supply Voltage
0V
Internal Reset Signal (RES)
Wait * (Approx. 31.3 ms:4.19 MHz)
HALT Mode
Operating Mode
Internal Reset Operation
Figure 8-3 Reset Operation by Reset Input
Wait * (Approx. 31.3 ms:4.19 MHz)
RESET Input
Operation or Standby Mode
HALT Mode
Operating Mode
Internal Reset Operation
*:
The wait time does not include a time from the generation of RES signal to the start of oscillation.
Each hardware status after reset operation is shown in Table 8-1.
27
PD75112(A), 75116(A)
Table 8-1 Hardware Statuses after Reset
Hardware RESET Input in Standby Mode RESET Input in Power-On Reset or Operation same as left
Program counter (PC)
Lower 6 bits of address 0000H of the program memory are set to PC13 to PC8 and the content of address 0001H is set to PC7 to PC0. Hold 0 0 Bits 6 and 7 of address 0000H of the program memory are set to RBE and MBE, respectively. Undefined Hold *1 Hold 0, 0 Undefined 0 0 FFH 0 0, 0 Hold 0 0
PWS
Carry flag (CY) Skip flag (SK0 to SK2) Interrupt status flag (IST0, 1) Bank enable flags (MBE, RBE)
Undefined 0 0 same as left
Stack pointer (SP) Data memory (RAM) General registers (X, A, H, L, D, E, B, C) Bank select registers (MBS, RBS)
Undefined Undefined Undefined 0, 0 Undefined 0 0 FFH 0 0, 0 Undefined 0 0
Basic interval timer
Counter (BT) Mode register (BTM)
Timer/ event counter (n = 0, 1)
Counter (Tn) Modulo register (TMODn) Mode register (TMn) TOEn, TOFn
Serial interface
Shift register (SIO) Mode register (SIOM)
Clock generator, clock output circuit Interrupt
Processor clock control register (PCC) Clock output mode register (CLOM) Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Priority select resister (IPS) INT0, 1 mode resisters (IM0, IM1)
0 Reset (0) 0 0 0, 0 Off Clear (0) 0 Undefined 0 Hold 0
0 Reset (0) 0 0 0, 0 Off Clear (0) 0 Undefined 0 1 or undefined *2 0
Digital port
Output buffer Output latch Input/output mode registers (PMGA, PMGB, PMGC)
Analog port
PTH00 to PTH03 input latches Mode register (PTHM)
Power-on flag (PONF) Bit sequential buffers (BSB0 to BSB3)
* 1: Power-on reset ................... 1 RESET input in operation ... Undefined 2: Data at addresses 0F8H to 0FDH of the data memory becomes undefined due to RESET input.
28
PD75112(A), 75116(A)
9. Instruction Set
(1) Operand identifier and description method In the operand column of each instruction, describe the corresponding operand in accordance with the description method for the operand identifier of the instruction (refer to the "RA75X Assembler Package User's Manual Language Volume" (EEU-730) for details). If more than one description method is available, select one of them. Capital alphabetic letters, plus and minus signs are key words. Describe them as they are. In the case of immediate data, describe appropriate numeric values or labels. Symbols of various registers and flags can be described as labels instead of mem, fmem, pmem, bit, etc. (Refer to the "PD751xx Series User's Manual (IEM922)" for details). Labels which can be described are limited for fmem and pmem.
Identifier reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label* 2-bit immediate data or label FB0H to FBFH and FF0H to FFFH immediate data or labels FC0H to FFFH immediate data or labels Description Method
PD75112(A) 0000H to 2F7FH immediate data or labels PD75116(A) 0000H to 3F7FH immediate data or labels
caddr faddr taddr PORTn IExxx RBn MBn
12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (bit = 0) or labels PORT0 to PORT9, PORT12 to PORT14 IEBT, IESIO, IET0, IET1, IE0 to IE4 RB0 to RB3 MB0, MB1, MB15
*: In the case of 8-bit data processing, only even address can be described for "mem".
29
PD75112(A), 75116(A)
(2) Legend in the description of operations A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx ) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : A register; 4-bit accumulator B register C register D register E register H register L register X register Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Extended register pair (XA') Extended register pair (BC') Extended register pair (DE') Extended register pair (HL') Program counter Stack pointer Carry flag; bit accumulator Program status word Memory bank enable flag Register bank enable flag Port n (n = 0 to 9, 12 to 14) Interrupt mask enable flag Interrupt priority select register Interrupt enable flag Register bank select register Memory bank select register Processor clock control register Address and bit division Content addressed by xx Hexadecimal data
30
PD75112(A), 75116(A)
(3) Description of symbols in the addressing area column
*1 MB=MBE*MBS (MBS=0, 1, 15) MB=0
*2
*3
MBE=0 : MB=0 (00H-7FH) MB=15 (80H-FFH) MBE=1 : MB=MBS (MBS=0, 1, 15)
Data Memory Addressing
*4
MB=15, fmem=FB0H-FBFH, FF0H=FFFH MB=15, pmem=FC0H-FFFH addr=0000H-2F7FH (PD75112(A)) =0000H-3F7FH (PD75116(A))
*5 *6
*7
addr=(Current PC) -15 to (Current PC) +16
*8
caddr=0000H-0FFFH (PC13, PC12=00B =1000H-1FFFH (PC13, PC12=01B =2000H-2F7FH (PC13, PC12=10B =2000H-2FFFH (PC13, PC12=10B =3000H-3F7FH (PC13, PC12=11B
: : : : :
PD75112(A), 116(A)) or PD75112(A), 116(A)) or PD75112(A)) or PD75116(A)) or PD75116(A))
Program Memory Addressing
*9 *10
faddr=0000H-07FFH taddr=0020H-007FH
Remarks 1: MB indicates an accessible memory bank. 2: In *2, MB = 0 irrespectively of MBE and MBS. 3: In *4 and *5, MB = 15 irrespectively of MBE and MBS. 4: *6 to *10 indicate addressable areas.
One machine cycle is equal to one cycle (=tCY)of CPU clock. Three values are available for the one machine cycle by PCC setting.
(4) Description of machine cycle column S indicates the number of machine cycles required for the instruction having skip function to execute skip operation. The value of S varies as follows: * When no skip ............................................. S = 0 * When 1-byte or 2-byte instruction is skipped ................................................. S = 1 * When 3-byte instruction (BR !addr, CALL !addr instructions) is skipped ............................. S = 2 Note: GETI instruction is skipped in one-machine cycle. 31
PD75112(A), 75116(A)
Instructions Transfer Mnemonic MOV Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HLA, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1 XA XCH A, @HL A, @HL+ A, @HLA, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' Table Reference MOVT XA, @PCDE XA, @PCXA Bit Transfer MOV1 CY, fmem. bit CY, pmem. @L CY, @H+mem. bit fmem. bit, CY pmem. @L, CY @H+mem. bit, CY No. of Bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 2 2 2 2 2 2 Machine Cycle 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 2 2 2 2 2 2 An4 reg1n4 XAn8 HLn8 rp2n8 A(HL) A(HL), then LL+1 A(HL), then LL-1 A(rpa1) XA(HL) (HL)A (HL)XA A(mem) XA(mem) (mem)A (mem)XA Areg XArp' reg1A rp'1XA A(HL) A(HL), then LL+1 A(HL), then LL-1 A(rpa1) XA(HL) A(mem) XA(mem) Areg1 XArp' XA(PC13-8+DE)ROM XA(PC13-8+XA)ROM CY(fmem.bit) CY(pmem7-2+L3-2.bit(L1-0)) CY(H+mem3-0.bit) (fmem.bit)CY (pmem7-2+L3-2.bit(L1-0))CY (H+mem3-0.bit)CY *4 *5 *1 *4 *5 *1 *1 *1 *1 *2 *1 *3 *3 L=0 L=FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L=FH Stack A Stack B Operation Addressing Area Skip Condition Stack A
32
PD75112(A), 75116(A)
Instructions Arithmetic Mnemonic ADDS Operand A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA Accumulator Operation RORC NOT Increase/ Decrease INCS A A reg rp1 @HL mem DECS reg rp' Compare SKE reg, #n4 @HL, #n4 A, @HL No. of Bytes 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 1 Machine Cycle 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S Operation AA+n4 XAXA+n8 AA+(HL) XAXA+rp' rp'1rp'1+XA A, CYA+(HL)+CY XA, CYXA+rp'+CY rp'1, CYrp'1+XA+CY AA-(HL) XAXA-rp' rp'1rp'1-XA A, CYA-(HL)-CY XA, CYXA-rp'-CY rp'1, CYrp'1-XA-CY AAn4 AA(HL) XAXArp' rp'1rp'1XA AAn4 AA(HL) XAXArp' rp'1rp'1XA AAn4 AA(HL) XAXArp' rp'1rp'1XA CYA0, A3CY, An-1An AA regreg+1 rp1rp1+1 (HL)(HL)+1 (mem)(mem)+1 regreg-1 rp'rp'-1 Skip if reg=n4 Skip if (HL)=n4 Skip if A=(HL) *1 *1 *1 *3 reg=0 rp1=00H (HL)=0 (mem)=0 reg=FH rp'=FFH reg=n4 (HL)=n4 A=(HL) *1 *1 *1 *1 *1 borrow borrow borrow *1 *1 Addressing Area Skip Condition Carry Carry Carry Carry Carry
33
PD75112(A), 75116(A)
Instructions Compare Mnemonic SKE Operand XA, @HL A, reg XA, rp' Carry Flag Operation SET1 CLR1 SKT NOT1 CY CY CY CY No. of Bytes 2 2 2 1 1 1 1 Machine Cycle 2+S 2+S 2+S 1 1 1+S 1 Operation Skip if XA=(HL) Skip if A=reg Skip if XA=rp' CY1 CY0 Skip if CY=1 CYCY CY=1 Addressing Area *1 Skip Condition XA=(HL) A=reg XA=rp'
34
PD75112(A), 75116(A)
Instructions
Memory Bit Manipulation
Mnemonic SET1
Operand mem. bit fmem. bit pmem. @L @H+mem. bit
No. of Bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Machine Cycle 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S (mem.bit)1
Operation
Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5
Skip Condition
(fmem.bit)1 (pmem7-2+L3-2.bit(L1-0))1 (H+mem3-0.bit)1 (mem.bit)0 (fmem.bit)0 (pmem7-2+L3-2.bit(L1-0))0 (H+mem3-0.bit)0 Skip if (mem.bit)=1 Skip if (fmem.bit)=1 Skip if (pmem7-2+L3-2.bit(L1-0))=1 Skip if (H+mem3-0.bit)=1 Skip if (mem.bit)=0 Skip if (fmem.bit)=0 Skip if (pmem7-2+L3-2.bit(L1-0))=0 Skip if (H+mem3-0.bit)=0 Skip if (fmem.bit)=1 and clear Skip if (pmem7-2+L3-2.bit(L1-0)) =1 and clear Skip if (H+mem3-0.bit)=1 and clear CY CY(fmem.bit) CY CY(pmem7-2+L3-2.bit(L1-0)) CY CY(H+mem3-0.bit) CY CY(fmem.bit) CY CY(pmem7-2+L3-2.bit(L1-0)) CY CY(H+mem3-0.bit) CY CY(fmem.bit) CY CY(pmem7-2+L3-2.bit(L1-0)) CY CY(H+mem3-0.bit) PC13-0 addr (Most appropriate instruction is selected by assembler from among BR !addr, BRCB !caddr and BR $addr)
CLR1
mem. bit fmem. bit pmem. @L @H+mem. bit
SKT
mem. bit fmem. bit pmem. @L @H+mem. bit
(mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1
SKF
mem. bit fmem. bit pmem. @L @H+mem. bit
SKTCLR
fmem. bit pmem. @L
@H+mem. bit AND1 CY, fmem. bit CY, pmem. @L CY, @H+mem. bit OR1 CY, fmem. bit CY, pmem. @L CY, @H+mem. bit XOR1 CY, fmem. bit CY, pmem. @L CY, @H+mem. bit Branch BR addr
2 2 2 2 2 2 2 2 2 2
2+S 2 2 2 2 2 2 2 2 2
*1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *6
(@H+mem.bit)=1
!addr $addr BRCB BR !caddr PCDE PCXA
3 1 2 2 2
3 2 2 3 3
PC13-0 addr PC13-0 addr PC13-0PC13, 12+caddr11-0 PC13-0 PC13-8+DE PC13-0 PC13-8+XA
*6 *7 *8
35
PD75112(A), 75116(A)
Instructions
Subroutine Stack Control
Mnemonic CALL
Operand !addr
No. of Bytes 3
Machine Cycle 3
Operation (SP-4)(SP-1)(SP-2)PC11-0 (SP-3)MBE, RBE, PC13, 12 PC13-0addr, SPSP-4 (SP-4)(SP-1)(SP-2)PC11-0 (SP-3)MBE, RBE, PC13, 12 PC13-000, faddr, SPSP-4 MBE, RBE, PC13, 12(SP+1) PC11-0(SP)(SP+3)(SP+2) SPSP+4 MBE, RBE, PC13, 12(SP+1) PC11-0(SP)(SP+3)(SP+2) SPSP+4, then skip unconditionally PC13, 12(SP+1) PC11-0(SP)(SP+3)(SP+2) PSW(SP+4)(SP+5), SPSP+6 (SP-1)(SP-2)rp, SPSP-2 (SP-1)MBS, (SP-2)RBS, SPSP-2 rp(SP-1)(SP), SPSP-2 MBS(SP+1), RBS(SP), SPSP+2 IME (IPS.3)1 IExxx1 IME (IPS.3)0 IExxx0 APORTn (n=0-9, 12-14)
Addressing Area *6
Skip Condition
CALLF
!faddr
2
2
*9
RET
1
3
RETS
1
3+S
Unconditional
RETI
1
3
PUSH
rp BS
1 2 1 2 2
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3
POP
rp BS
Interrupt Control
EI IExxx DI IExxx
2 2 2 2 2 2 2 2 2 1
Input/Output
IN*1
A, PORTn XA, PORTn
XAPORTn+1, PORTn (n=4, 6, 8, 12) PORTn4 (n=2-9, 12-14)
OUT*1
PORTn, A PORTn, XA
PORTn+1, PORTnXA (n=4, 6, 8, 12) Set HALT Mode (PCC.21) Set STOP Mode (PCC.31) No Operation RBSn(n=0-3) MBSn (n=0, 1, 15) *10
CPU Control
HALT STOP NOP
Special
SEL
RBn MBn
2 2 1
GETI*2
taddr
* TBR Instruction PC13-0(taddr)4-0+(taddr+1) * TCALL Instruction (SP-4)(SP-1)(SP-2)PC11-0 (SP-3)MBE, RBE, PC13, 12 PC13-0(taddr)5-0+(taddr+1) SPSP-4 * When not TBR and TCALL instructions, (taddr) and (taddr+1) instructions are executed.
Depends on the instruction referred to.
* 1: MBE=0 or 1 and MBS=15 must be set for execution of IN/OUT instruction. , 2: TBR and TCALL instructions are assembler pseudo-instructions for GETI instruction table definition.
36
PD75112(A), 75116(A)
10. Mask Option Selection
The following mask options are available for the 5 PD75116(A). Whether or not they should be incorporated can be selected. (1) Pins
Pin P120 to P123 P130 to P133 P140 to P143 Mask Option Bit-wise pull-up resistor incorporation enable
(2) Power-on reset circuit and power-on flag (PONF) One of the following three settings can be selected.
Mask Option Specification Switch Selection (See Figure 8-1) SWA ON ON OFF SWB ON OFF OFF Generated automatically Not generated automatically Internal Reset Signal (RES)
Power-on Reset Circuit Incorporated Not incorporated Not incorporated
Power-on Flag (PONF) Incorporated Incorporated Not incorporated
37
PD75112(A), 75116(A)
11. Electrical Specifications
Absolute Maximum Ratings (Ta = 25 C)
Parameter Power supply voltage Input voltage Symbol VDD VI1 VI2 *1 Except for ports 12 to 14 Ports 12 to 14 On-chip pull-up resistor Open drain Output voltage Output current high VO IOH 1 pin Peak value Effective value All pins Peak value Effective value Output current low IOL *2 1 pin Peak value Effective value Total current of ports 0, 2 to 4, 12 to 14 Peak value Effective value Peak value Effective value Operation temperature Storage temperature Topt Tstg Test Conditions Ratings -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to +13 -0.3 to VDD +0.3 -10 -5 -30 -15 10 5 50 25 50 25 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA C C
* 1: When applying a voltage larger than 10 V to ports 12, 13 and 14 each, set the power impedance (pull-up resistor) to 50 k or more. 2: Calculate each effective value using the following expression: [Effective value]=[Peak value] x duty
Note: Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
38
PD75112(A), 75116(A)
Operating Voltage 5 (Ta = -40 to +85 C)
Parameter CPU*1 Programmable threshold port (comparator input) Power-on reset circuit*3 Other hardware*1 Test Conditions MIN. *2 4.5 4.5 2.7 MAX. 6.0 6.0 6.0 6.0 Unit V V V V
* 1: Except system clock oscillator, programmable threshold port and power-on reset circuit 2: Operating voltage range depends on the cycle time. See the AC Characteristics. 3: Whether or not it should be incorporated can be selected by mask options. See the Power-On Reset Circuit Characteristics (Mask Option).
39
PD75112(A), 75116(A)
Oscillate Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Oscillator Ceramic oscillation
X1 X2
Recommended Constant
Parameter Oscillator frequency (fXX)*1
Test Condition VDD = oscillation voltage range
MIN. 2.0
TYP.
MAX. 5.0*3
Unit MHz
C1
C2
Oscillation stabilizing time*2
Oscillation voltage range MIN.
4
ms
Crystal oscillator
X1 X2
Oscillator frequency (fXX)*1
2.0
4.19
5.0*3
MHz
C1
C2
Oscillation stabilizing time*2
VDD = 4.5 to 6.0 V
10
ms
30
ms
External clock
X1 input frequency (fX)*1
2.0
5.0*3
MHz
X1
X2
PD74HCU04
X1 input high and low level widths (tXH, tXL)
100
250
ns
5
* 1: Oscillator frequency and X1 input frequency indicate only characteristics of the oscillator. Refer to AC characteristics for the instruction execution time. 2: The oscillation stabilizing time is necessary for oscillation to stabilize after VDD reaches oscillation voltage range MIN. or the STOP mode is released. 3: When the oscillator frequency is 4.19 MHz < fXX 5.0 MHz, PCC=0011 should not be selected as instruction execution time. If PCC=0011 is selected, 1 machine cycle becomes less than 0.95 s, with the result that the specified MIN. value of 0.95 s cannot be observed.
Note: When using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS. Do not ground wiring to a ground pattern in which a high current flows. * Do not fetch a signal from the oscillator.
5
40
PD75112(A), 75116(A)
DC Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Input voltage high Symbol VIH1 VIH2 VIH3 Test Conditions Except for ports listed below Ports 0, 1, TI0, 1, RESET Ports 12 to 14 On-chip pull-upresistor Open drain VIH4 Input vltage low VIL1 VIL2 VIL3 Output voltage high VOH X1, X2 Except for ports listed below Ports 0, 1, TI0, 1, RESET X1, X2 VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100A Output voltage low VOL VDD = 4.5 to 6.0 V Ports 0, 2 to 9, IOL = 5 mA Ports 12 to 14, IOL = 5 mA VDD = 4.5 to 6.0V, IOL = 1.6 mA IOL = 400A Input leakage current high ILIH1 ILIH2 ILIH3 Input leakage current low ILIL1 ILIL2 Output leakage current high ILOH1 ILOH2 Output leakage current low On-chip pull-up resistor ILOL RL VOUT = VDD VOUT = 12 V VOUT = 0 V Ports 12 to 14 VDD=5 V 10% 15 10 Supply current*1 IDD1 4.19 MHz crystal oscillation C1 = C2 = 22 pF VDD=5 V 10%*2 VDD=3 V 10%*3 HALT mode VDD=5 V 10% VDD=3 V 10% IDD3 STOP mode, VDD = 3 V 10% 3 0.55 600 200 0.1 40 VIN = 12 V VIN = 0 V VIN = VDD Except for ports listed below X1, X2 Ports 12 to 14 (for open drain) Except for X1, X2 X1, X2 Except for ports listed below Ports 12 to 14 (for open drain) MIN. 0.7VDD 0.8VDD 0.7VDD 0.7VDD VDD-0.5 0 0 0 VDD-1.0 VDD-0.5 0.25 0.40 1.0 1.0 0.4 0.5 3 20 20 -3 -20 3 20 -3 70 80 9 1.5 1800 600 10 TYP. MAX. VDD VDD VDD 12 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V V V V V
A A A A A A A A
k k mA mA
IDD2
A A A
* 1: Current for the on-chip pull-up resistor, power-on reset circuit (mask option) and comparator circuit is not included. 2: When operated in the hgh-speed mode with the processor clock
control resistor (PCC) set tp 0011. 3: When operated in the low-speed mode with the PCC set to 0000.
41
PD75112(A), 75116(A)
Capacitance (Ta = 25 C, VDD = 0 V)
Parameter Input capacitance Output capacitance Input/output capacitance Symbol CIN COUT CIO Test Conditions f = 1 MHz 0 V for pins except the measured pins MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Comparator Characteristics (Ta = -40 to +85 C, VDD = 4.5 to 6.0 V)
Parameter Comparison accuracy Threshold voltage PTH input voltage Comparator circuit consumption Symbol VACOMP VTH VIPTH Set PTHM7 to "1". 0 0 1 Test Conditions MIN. TYP. MAX. 100 V DD VDD Unit mV V V mA
Power-On Reset Circuit Characteristics (Mask Option) (Ta = -40 to +85 C)
Parameter Power-on reset operating voltage high Power-on reset operating voltage low Supply voltage rise time Supply voltage off time Power-on reset circuit current consumption*2 Symbol VDDH VDDL tr toff VDD = 5 V 10% IDDPR VDD = 2.5 V 2 20 Test Conditions MIN. 4.5 0 10 1 10 100 TYP. MAX. 6.0 0.2 *1 Unit V V
s
s
A A
*1: 217/fXX (31.3 ms when fXX = 4.19MHz) 2: Current flow upon power-on reset or with an on-chip power-on flag
VDDH VDD VDDL
toff
tr
Note: Start the power supply smoothly. 42
PD75112(A), 75116(A)
AC Characteristics (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter CPU clock cycle time* (min. instruction execution time = 1 machine cycle) TI0, TI1 input frquency Symbol tCY Test Conditions VDD = 4.5 to 6.0 V MIN. 0.95 3.8 fTI VDD = 4.5 to 6.0 V 0 0 TI0, TI1 input high and low-level widths tTIH, tTIL VDD = 4.5 to 6.0 V 0.48 1.8 SCK cycle time tKCY VDD = 4.5 to 6.0 V Input Output Input Output SCK high and low-level widths tKH, tKL VDD = 4.5 to 6.0 V Input Output Input Output SI setup time (to SCK) SI hold time (from SCK) S0 output delay time from SCK tSIK tKSI tKSO VDD = 4.5 to 6.0 V 0.8 0.95 3.2 3.8 0.4 tKCY/2-50 1.6 tKCY/2-50 100 400 300 1000 INT0 to INT4 High and low-level widths RESET low-level sidth tINTH, tINTL tRSL 5 5 TYP. MAX. 32 32 1 275 Unit
s s
MHz kHz
s s s s s s s
ns
s
ns ns ns ns ns
s s
43
PD75112(A), 75116(A)
*: The cycle time of the CPU clock ( ) is determined by the input frequency of the ceramic crystal oscillator and the setting of the processor clock control register (PCC). The cycle time (tCY) for VDD is shown below.
tCY vs. VDD [V] 40 32 7 6 5 4
Cycle Time tCY [ s]
3
Operation Guaranteed Range
2
1
0.5
0
1
2
3
4
5
6
Supply Voltage VDD [V]
AC Timing Test Point (Except for Ports 0, 1, TI0, TI1, X1, X2 and RESET)
0.7 VDD 0.3 VDD
Test Points
0.7 VDD 0.3 VDD
Clock Timing
1/fX
tXL
tXH VDD - 0.5 0.4
X1 Input
44
PD75112(A), 75116(A)
TI0 and TI1 Input Timing
1/fTI
tTIL TI0, TI1
tTIH 0.8 VDD 0.2 VDD
Serial Transfer Timing
tKCY tKL tKH
0.8 VDD SCK 0.2 VDD
tSIK
tKSI
SI
0.8 VDD Input Data 0.2 VDD
tKSO
SO
Output Data
Interrupt Input Timing
tINTL INT0-INT4 0.8 VDD 0.2 VDD
tINTH
45
PD75112(A), 75116(A)
RESET Input Timing
tRSL
RESET
0.2 VDD
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (Ta = -40 to +85 C)
Parameter Data retention supply voltage Data retention supply current*1 Release signal set time Oscillation stabilization wait time*2 Symbol VDDDR VDDDR tSREL tWAIT Release by RESET Release by interrupt request VDDDR = 2.0 V 0 217/fX *3 Test Conditions MIN. 2.0 0.1 TYP. MAX. 6.0 10 Unit V
A s
ms ms
* 1: Current for the on-chip pull-up resistor, power-on circuit (mask option) and comparator circuit is not included. 2: The oscillation stabilizing time is intended to stop the CPU to prevent any unstable operation at the start of oscillation. 3: Depends on the following setting of the basic interval timer mode register (BTM).
BTM3
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1
Wait Time (fXX=4.19 MHz Valus in Parentheses) 220/fXX (approx. 250 ms) 217/fXX (approx. 31.3 ms) 215/fXX (approx. 7.82 ms) 213/fXX (approx. 1.95 ms)
46
PD75112(A), 75116(A)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
Standby Release Signal (Interrupt Request) tWAIT
47
PD75112(A), 75116(A)
12. Packing Information
64 PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J
I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
48
PD75112(A), 75116(A)
64 PIN PLASTIC (14 x 20) (Unit: 64-Pin Plastic QFP QFP (14x20) mm) 5
A B
51 52
33 32
detail of lead end
C
D
S
64 1
20 19
F
G
H
IM
J
K
P
N L P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.40 0.10 0.20 1.0 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.12 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.071-0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.005 0.106 0.004 0.004 0.119 MAX.
+0.008
M
55
Q
49
PD75112(A), 75116(A)
13. Recommended Soldering Conditions
5
The PD75112(A) and 75116(A) should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document "Surface Mount Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our sales personnel.
Table 13-1 Surface Mounting Type Soldering Conditions
PD75112GF(A)-xxx-3BE : 64-pin plastic QFP (14 x 20mm) PD75116GF(A)-xxx-3BE : 64-pin plastic QFP (14 x 20mm)
Soldering Method Infrared reflow VPS Soldering Conditions Package peak temperature: 230 C Duration: 30 sec. max. (at 210C above) Number of times: Once Package peak temperature: 215 C Duration: 40 sec. max. (at 200C above) Number of times: Once Solder bath temperature: 260 C max. Duration: 10 sec. max. Number of times: Once Preliminary heat temperature: 120 C max. (Package surface temperature) Pin part temperature: 300 C max. Duration: 3 sec. max. (per device side) Recommended Condition Symbol IR30-00-1
VP15-00-1
Wave soldering
WS60-00-1
Pin part heating
Note: Use more than one soldering method should be avoided (except in the case of pin part).
Table 13-2 Insertion Type Soldering Conditions
PD75112CW(A)-xxx: 64-pin plastic shrink DIP (750 mil) PD75116CW(A)-xxx: 64-pin plastic shrink DIP (750 mil)
Soldering Method Wave soldering (lead part only) Pin part heating Soldering Conditions Solder bath temperature: 260 C max. Duration: 10 sec. max. Pin part temperature: 260 C max. Duration: 10 sec. max.
Note: Wave soldering is only for the lead part in order that jet solder can not contact with the chip.
Notice
A version of this product with improved recommended soldering conditions is available. For details (improvements such as infrared reflow peak temperature extension (235 C, number of times: twice, relaxation of time limit), contact NEC sales 51
PD75112(A), 75116(A)
5
APPENDIX A. Differences between PD751xx(A) Series Products and Related PROM Products
Product Name Item ROM Configuration ROM (bit) 0000H to 0FFFH 4096 x 8 0000H to 177FH 6016 x 8
PD75104(A)
PD75106(A)
PD75108(A) PD75112(A)
Mask ROM 0000H to 1F7FH 8064 x 8 0000H to 2F7FH 12160 x 8 512 x 4 Bank 0: 256 x 4 Bank 1: 256 x 4
PD75116(A)
PD75P108B
PD75P116
PROM 0000H to 3F7FH 16256 x 8 0000H to 1F7FH 8064 x 8 0000H to 3F7FH 16256 x 8
RAM (bit)
320 x 4 Bank 0: 256 x 4 Bank 1: 64 x 4
512 x 4 Bank 0: 256 x 4 Bank 1: 256 x 4 High end
Instruction set I/O line Total Input/ output
High end (Only PD75104(A) does not incorporate BR !addr instruction). 58 * CMOS input/output: 32 * +12 V withstand N-ch voltage open-drain input/output: 12 (Pull-up resistor can be on-chip by mask option.)
* CMOS input/output: 32 * +12 V withstand N-ch open-drain input/ output: 12 Each pin can directly drive LED: 44
Input
* CMOS input/output: 10 * Comparator: 4 Can be on-chip by mask option None
Power-on reset circuit Power-on flag Supply voltage range Pin connection
2.7 to 6.0 V Differs depending on package
2.7 to 6.0 V
5 V10%
Differs depending on package (with VPP pin) Standard * 64-pin plastic * 64-pin plastic shrink DIP shrink DIP (750 mil) (750 mil) * 64-pin ceramic * 64-pin plastic QFP shrink DIP (with window) (14 x 20 mm) * 64-pin plastic QFP (14 x 20 mm)
Quality grade Package * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm)
Special
52
PD75112(A), 75116(A)
APPENDIX B. Development Tools
The following tools are available for the development of systems for which the PD75116(A) is used.
Hardware IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 EP-75108CW-R EP-75108GF-R EV-9200G64 PG-1500 PA-75P108CW PA-75P116GF Software IE control program PG-1500 controller RA75X relocatable assembler PROM programmer 75X series in-circuit emulator
Emulation board for IE-75000R and IE-75001-R. Emulation probe for PD75112CW(A) and 75116CW(A). Emulation probe for PD75112GF(A) and 75116GF(A). 64-pin conversion socket EV-9200G64 added.
PD75P116CW PROM programmer adapter connected to PG-1500 PD75P116GF PROM programmer adapter connected to PG-1500
Host machine * PC-9800 series (MS-DOSTM Ver. 3.30 to 5.00A*3) * IBM PC/ATTM (PC DOSTM Ver. 3.1)
* 1: Maintenance product 2: Not incorporated in the IE-75001-R. 3: The task swap function, which is provided with Ver. 5.00/5.00A, is not available with this software.
Remarks: For development tools manufactured by a third party, see the "75X Series Selection Guide" (IF-151)".
53
PD75112(A), 75116(A)
5
APPENDIX C. Related Documentations
List of Device Related Documentations
Document Name User's Manual Instruction Application Table Application Note (I) Introductory Volume (II) Remote Control Reception Volume (III) Bar-Code Reader Volume (IV) IC Control for MSK Transmission/Reception Volume 75X Series Selection Guide Document Number IEM-1260 -- IEM-1139 IEM-1281 IEM-1265 IEA-1278 IF-1027
List of Development Tools Related Documentations
Document Name Hardware IE-75000-R/IE-75001-R User's Manual IE-75000-R-EM User's Manual EP-75108CW-R User's Manual EP-75108GF-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual Operation Volume Language Volume PG-1500 Controller User's Manual Document Number EEU-1416 EEU-1294 EEU-1308 EEU-1318 EEU-1335 EEU-1346 EEU-1343 EEU-1291
List of Other Related Documentations
Document Name Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guarantee Guide Microcomputer Related Products Guide Other Manufactures Volume Document Number IEI-1213 IEI-1207 IEI-1209 -- -- MEI-1202 --
Note: The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 54
PD75112(A), 75116(A)
55
PD75112(A), 75116(A)
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may ppear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual propety rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporations.

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